The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a memory integrated circuit (IC) 10 is shown. The memory IC 10 comprises a memory array 12, a decoder 14, and a state sensing circuit 16. The memory array 12 includes an array of memory cells 15. The decoder 14 selects one of the memory cells 15 of the memory array 12. The state sensing circuit 16 senses a state of the selected memory cell 15.
Specifically, the state sensing circuit 16 comprises a voltage source 17 that applies a voltage difference across first and second bit lines (not shown) that are connected to the selected memory cell. The state sensing circuit 16 senses current that flows through the selected memory cell (Icell). The value of Icell changes depending on the state of the selected memory cell. Typically, the state sensing circuit 16 utilizes a sense amplifier 18 that senses a voltage drop Vcell generated by Icell. The sense amplifier 18 compares Vcell to a reference voltage Vref. For binary memory cells, the sense amplifier 18 determines the state of the selected memory cell based on whether Vcell is greater or less than Vref.
Referring now to FIG. 2, a typical sense amplifier 50 is shown. The sense amplifier 50 uses a latch-type structure comprising two mirrored circuits, each comprising a differential pair of transistors. Specifically, a first differential pair of transistors Q1 and Q2 is cross-coupled to a second differential pair of transistors Q3 and Q4 as shown. Vcell and Vref are input to transistors Q3 and Q4, respectively. The transistors Q3 and Q4 represent two inputs or two input paths of the sense amplifier 50. One input or input path (e.g., Q3) is used for sensing Vcell while another input or input path (e.g., Q4) is used for sensing Vref.
The sense amplifier 50 compares Vcell to Vref and generates outputs V1 and V2 that indicate the state of the selected memory cell. For example, V1 may be positive and V2 may be negative indicating that the state of the selected memory cell is a binary 1 when Vcell>Vref. Conversely, V1 may be negative and V2 may be positive indicating that the state of the selected memory cell is a binary 0 when Vcell<Vref.